Monday, 2 September 2013

3D–INTEGRATED CIRCUIT : The New Emerging Technology in CHIP Design Industry


Over the decades, Moore's law, which states that over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years, has continued mapping into reality since from it was stated. This has been proven accurate in the Semiconductor Industry. The capabilities of many digital electronic devices are strongly linked to Moore's law: processing speed, memory capacity, sensors and even the number and size of pixels in digital cameras. Also the capabilities of all these devices are improving exponentially as well.
In the past basically System on Chip (SoC) components allowed the integration of many functionalities. But the rapid downsizing as per Moore’s law CMOS technology reaches limits and SoC solutions request commercially high production volume. This implies that the packaging density of an IC has continued to increase day by day, thereby the performance per IC has also continued to increase with ease; therefore the methods to develop solutions to produce IC other than on a 2D structure were not sought.
The improvements in the on-chip wire delay and in the maximum no. of inputs and outputs per chip have not been able to keep up with transistor performance growth, and it has become progressively harder to hide the discrepancy. In addition, the complexities of lithography beyond the 32 nm node threaten the traditional performance and cost scaling patterns. In contrast with these conventional 2D structure, 3D IC offers a new pattern that builds multiple layers of active devices stacked over each other.
Now days the 3D ICs have recently getting attention among the researchers and IC designers as an cutting-edge technology to overcome the issues related to interconnect delay and power limitations. The evolution of 3D IC technology shows promising possibilities for the future of chip design with some tremendous advantages: Lower Power Consumption, Short Delays, Less interconnects Length, Capacitance, Resistance, Low Foot Print, Improved System Performance.

  • The first person who had given the concept about 3D Integrated Circuits was Prof. Jim Early of Bell Labs. In 1960, he had stated about the stacking components in a Cubic Arrangements.
  • In 2004, Intel presented a 3D version of the Pentium 4 CPU. It was manufactured with two dies using face-to-face stacking, which thereby enabled a dense via structure. Backside TSVs are used for I/O and power supply.
  • The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional I/O approach would consume 10 to 25 W.
  • The academic implementation of 3D processor was first introduced by Prof. Eby Friedman & his students in the year 2008 at University of Rochester.
  • Two 3D-IC-based multi-core designs using GlobalFoundries' 130 nm process and Tezzazon's FaStack technology were presented and demonstrated in ISSCC 2012.
  • One of the major Semiconductor industry giant Synopsys, introduced a 3D-IC solution in the first half of 2012.
 Following are the technologies used for building 3D ICs.
  • Monolithic: in this process electronic components and their interconnects are placed on a single layer of Semiconductor Wafer, which is then diced in to 3D ICs. In this process there is no need for thinning, aligning, bonding or through-Silicon Vias as there is only one substrate.
  • Wafer on Wafer: in this process, electronic components are built on two or more Semiconductor Wafers, which are then aligned, bonded and diced in to 3D ICs.
  • Die on Wafer: in this process, electronic components are built on two wafers. One wafer is diced, then the singulated dice are aligned & bonded on to the die sites of second wafer.
  • Die on Die: in this process, electronic components are built on multiple dice, which are then aligned and bonded.

  • Lower Footprints: by using the design of 3D ICs, it creates the ability to reduce the footprints of an existing IC. It implies more functionality can be implemented in to small space.
  • Lower Power Consumption: as per UC Davis's William Dally's 2006 presentation, placing a signal on a chip can actually contribute to a 10x to  100x reduction in power by the use of 3D IC.
  • Short Interconnect Delays: by using the 3-dimensional design the length between the interconnects are reduced on an average. It thereby reduces the delays between the interconnects.
  • Bandwidth: the 3-dimensional design allows large no of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks of different layers.
  • Cost: by partitioning a large chip on to multiple smaller dies with 3D stacking, reduces the number of interconnects, thereby results in high yield and reduces the fabrication cost.
  • Thermal Flux: stacking multiple active dies directly on top of each other leads to high concentration of heat, which cannot be easily dissipated.
  • Increased risk of defects: in 3D design new series of interconnects are need to implemented, which require thorough testing and verification because the failure of a single plane can result to the failure of entire IC.
  • Lack of design tools: implementation of 3D ICs require highly sophisticated design technologies and new CAD tools.
  • Lack of Standards: several options have been explored are some of them are currently under research but yet a de-facto for 3D IC development has yet to be introduced.

Though 3D ICs have several benefits of its predecessors but first careful consideration needs to be taken in getting the proper solution for the above said challenges that are inherent in adding a 3-dimension to a circuit design.
If high design standards and high automated design tools are properly implemented then in future it will bring tremendous result in Semiconductor industry with high productivity and improved performance.